\noindent 
\begin{tabular}{|p{1.5in}|p{3.5in}|p{0.5in}|p{0.5in}|}
\cline{1-4}
\texttt{disksim\_cachemem} & \texttt{Cache size} & int & required \\ 
\cline{1-4}
\multicolumn{4}{|p{6in}|}{
This specifies the total size of the cache in blocks.
}\\ 
\cline{1-4}
\multicolumn{4}{p{5in}}{}\\
\end{tabular}\\ 
\noindent 
\begin{tabular}{|p{1.5in}|p{3.5in}|p{0.5in}|p{0.5in}|}
\cline{1-4}
\texttt{disksim\_cachemem} & \texttt{SLRU segments} & list & optional \\ 
\cline{1-4}
\multicolumn{4}{|p{6in}|}{
This is a list of segment sizes in blocks for the segmented-LRU algorithm
\cite{Karedla94} if it is specified as the cache replacement algorithm
(see below).
}\\ 
\cline{1-4}
\multicolumn{4}{p{5in}}{}\\
\end{tabular}\\ 
\noindent 
\begin{tabular}{|p{1.5in}|p{3.5in}|p{0.5in}|p{0.5in}|}
\cline{1-4}
\texttt{disksim\_cachemem} & \texttt{Line size} & int & required \\ 
\cline{1-4}
\multicolumn{4}{|p{6in}|}{
This specifies the cache line size (i.e.,~the unit of cache space
allocation/replacement).
}\\ 
\cline{1-4}
\multicolumn{4}{p{5in}}{}\\
\end{tabular}\\ 
\noindent 
\begin{tabular}{|p{1.5in}|p{3.5in}|p{0.5in}|p{0.5in}|}
\cline{1-4}
\texttt{disksim\_cachemem} & \texttt{Bit granularity} & int & required \\ 
\cline{1-4}
\multicolumn{4}{|p{6in}|}{
This specifies the number of blocks covered by each ``present'' bit and
each ``dirty'' bit. The value must divide the cache line size evenly.
Higher values (i.e.,~coarser granularities) can result in increased
numbers of installation reads (i.e.,~fill requests required to
complete partial-line writes \cite{Otoole94}).
}\\ 
\cline{1-4}
\multicolumn{4}{p{5in}}{}\\
\end{tabular}\\ 
\noindent 
\begin{tabular}{|p{1.5in}|p{3.5in}|p{0.5in}|p{0.5in}|}
\cline{1-4}
\texttt{disksim\_cachemem} & \texttt{Lock granularity} & int & required \\ 
\cline{1-4}
\multicolumn{4}{|p{6in}|}{
This specifies the number of blocks covered by each lock. The value must
divide the cache line size evenly. Higher values (i.e.,~coarser
granularities) can lead to increased lock contention.
}\\ 
\cline{1-4}
\multicolumn{4}{p{5in}}{}\\
\end{tabular}\\ 
\noindent 
\begin{tabular}{|p{1.5in}|p{3.5in}|p{0.5in}|p{0.5in}|}
\cline{1-4}
\texttt{disksim\_cachemem} & \texttt{Shared read locks} & int & required \\ 
\cline{1-4}
\multicolumn{4}{|p{6in}|}{
This specifies whether or not read locks are sharable. If false~(0), read
locks are exclusive.
}\\ 
\cline{1-4}
\multicolumn{4}{p{5in}}{}\\
\end{tabular}\\ 
\noindent 
\begin{tabular}{|p{1.5in}|p{3.5in}|p{0.5in}|p{0.5in}|}
\cline{1-4}
\texttt{disksim\_cachemem} & \texttt{Max request size} & int & required \\ 
\cline{1-4}
\multicolumn{4}{|p{6in}|}{
This specifies the maximum request size to be served by the cache. This
value does not actually affect the simulated cache's behavior.
Rather, higher-level system components (e.g.,~the device driver in
DiskSim) acquire this information at initialization time and break up
larger requests to accommodate it. 0~indicates that there is no
maximum request size.
}\\ 
\cline{1-4}
\multicolumn{4}{p{5in}}{}\\
\end{tabular}\\ 
\noindent 
\begin{tabular}{|p{1.5in}|p{3.5in}|p{0.5in}|p{0.5in}|}
\cline{1-4}
\texttt{disksim\_cachemem} & \texttt{Replacement policy} & int & required \\ 
\cline{1-4}
\multicolumn{4}{|p{6in}|}{
This specifies the line replacement policy.
1~indicates First-In-First-Out (FIFO).
2~indicates segmented-LRU \cite{Karedla94}.
3~indicates random replacement.
4~indicates Last-In-First-Out (LIFO).
}\\ 
\cline{1-4}
\multicolumn{4}{p{5in}}{}\\
\end{tabular}\\ 
\noindent 
\begin{tabular}{|p{1.5in}|p{3.5in}|p{0.5in}|p{0.5in}|}
\cline{1-4}
\texttt{disksim\_cachemem} & \texttt{Allocation policy} & int & required \\ 
\cline{1-4}
\multicolumn{4}{|p{6in}|}{
This specifies the line allocation policy.
0~indicates that the cache replacement policy is strictly followed; if
the selected line is dirty, the allocation waits for the required
write-back request to complete.
1~indicates that ``clean'' lines are considered for replacement prior
to ``dirty'' lines (and background write-back requests are issued for
each dirty line considered).
}\\ 
\cline{1-4}
\multicolumn{4}{p{5in}}{}\\
\end{tabular}\\ 
\noindent 
\begin{tabular}{|p{1.5in}|p{3.5in}|p{0.5in}|p{0.5in}|}
\cline{1-4}
\texttt{disksim\_cachemem} & \texttt{Write scheme} & int & required \\ 
\cline{1-4}
\multicolumn{4}{|p{6in}|}{
This specifies the policy for handling write requests.
1~indicates that new data are always synchronously written to the
backing store before indicating completion.
2~indicates a write-through scheme where requests are immediately
initiated for writing out the new data to the backing store. The
original write requests are considered complete as soon as the new
data is cached.
3~indicates a write-back scheme where completions are reported
immediately and dirty blocks are held in the cache for some time
before being written out to the backing store.
}\\ 
\cline{1-4}
\multicolumn{4}{p{5in}}{}\\
\end{tabular}\\ 
\noindent 
\begin{tabular}{|p{1.5in}|p{3.5in}|p{0.5in}|p{0.5in}|}
\cline{1-4}
\texttt{disksim\_cachemem} & \texttt{Flush policy} & int & required \\ 
\cline{1-4}
\multicolumn{4}{|p{6in}|}{
This specifies the policy for flushing dirty blocks to the backing store
(assuming a write-back scheme for handling write requests).
0~indicates that dirty blocks are written back ``on demand''
(i.e.,~only when the allocation/replacement policy needs to reclaim
them).
1~indicates write-back requests are periodically initiated for all
dirty cache blocks.
}\\ 
\cline{1-4}
\multicolumn{4}{p{5in}}{}\\
\end{tabular}\\ 
\noindent 
\begin{tabular}{|p{1.5in}|p{3.5in}|p{0.5in}|p{0.5in}|}
\cline{1-4}
\texttt{disksim\_cachemem} & \texttt{Flush period} & float & required \\ 
\cline{1-4}
\multicolumn{4}{|p{6in}|}{
This specifies the time between periodic write-backs of all dirty cache
blocks (assuming a periodic flush policy).
}\\ 
\cline{1-4}
\multicolumn{4}{p{5in}}{}\\
\end{tabular}\\ 
\noindent 
\begin{tabular}{|p{1.5in}|p{3.5in}|p{0.5in}|p{0.5in}|}
\cline{1-4}
\texttt{disksim\_cachemem} & \texttt{Flush idle delay} & float & required \\ 
\cline{1-4}
\multicolumn{4}{|p{6in}|}{
This specifies the amount of contiguous idle time that must be observed
before background write-backs of dirty cache blocks are initiated.
Any front-end request processing visible to the cache resets the idle
timer. $-1.0$ indicates that idle background flushing is disabled.
}\\ 
\cline{1-4}
\multicolumn{4}{p{5in}}{}\\
\end{tabular}\\ 
\noindent 
\begin{tabular}{|p{1.5in}|p{3.5in}|p{0.5in}|p{0.5in}|}
\cline{1-4}
\texttt{disksim\_cachemem} & \texttt{Flush max line cluster} & int & required \\ 
\cline{1-4}
\multicolumn{4}{|p{6in}|}{
This specifies the maximum number of cache lines that can be combined into
a single write-back request (assuming ``gather'' write support).
}\\ 
\cline{1-4}
\multicolumn{4}{p{5in}}{}\\
\end{tabular}\\ 
\noindent 
\begin{tabular}{|p{1.5in}|p{3.5in}|p{0.5in}|p{0.5in}|}
\cline{1-4}
\texttt{disksim\_cachemem} & \texttt{Read prefetch type} & int & required \\ 
\cline{1-4}
\multicolumn{4}{|p{6in}|}{
This specifies the prefetch policy for handling read requests.
Prefetching is currently limited to extending requested fill accesses
to include other portions of requested lines.
0~indicates that prefetching is disabled.
1~indicates that unrequested data at the start of a requested line are
prefetched.
2~indicates that unrequested data at the end of a requested line are
prefetched.
3~indicates that any unrequested data in a requested line are
prefetched (i.e.,~full line fills only).
}\\ 
\cline{1-4}
\multicolumn{4}{p{5in}}{}\\
\end{tabular}\\ 
\noindent 
\begin{tabular}{|p{1.5in}|p{3.5in}|p{0.5in}|p{0.5in}|}
\cline{1-4}
\texttt{disksim\_cachemem} & \texttt{Write prefetch type} & int & required \\ 
\cline{1-4}
\multicolumn{4}{|p{6in}|}{
This specifies the prefetch policy for handling installation reads (caused
by write requests). Prefetching is currently limited to extending the
requested fill accesses to include other portions of the requested
lines.
0~indicates that prefetching is disabled.
1~indicates that unrequested data at the start of a requested line are
prefetched.
2~indicates that unrequested data at the end of a requested line are
prefetched.
3~indicates that any unrequested data in a requested line are
prefetched (i.e.,~full line fills only).
}\\ 
\cline{1-4}
\multicolumn{4}{p{5in}}{}\\
\end{tabular}\\ 
\noindent 
\begin{tabular}{|p{1.5in}|p{3.5in}|p{0.5in}|p{0.5in}|}
\cline{1-4}
\texttt{disksim\_cachemem} & \texttt{Line-by-line fetches} & int & required \\ 
\cline{1-4}
\multicolumn{4}{|p{6in}|}{
This specifies whether or not every requested cache line results in a
separate fill request. If false~(0), multi-line fill requests can be
generated when appropriate.
}\\ 
\cline{1-4}
\multicolumn{4}{p{5in}}{}\\
\end{tabular}\\ 
\noindent 
\begin{tabular}{|p{1.5in}|p{3.5in}|p{0.5in}|p{0.5in}|}
\cline{1-4}
\texttt{disksim\_cachemem} & \texttt{Max gather} & int & required \\ 
\cline{1-4}
\multicolumn{4}{|p{6in}|}{
This specifies the maximum number of non-contiguous cache lines (in terms
of their memory addresses)
%physically contiguous (but logically non-contiguous) cache lines
that can be combined into a single disk request, assuming that they
correspond to contiguous disk addresses. (DiskSim currently treats
every pair of cache lines as non-contiguous in memory.)
%Therefore,
%this value specifies the maximum number of cache lines that can be filled
%or cleaned by a single backing store access.)
0~indicates that any number of lines can be combined into a single
request (i.e.,~there is no maximum).
}\\ 
\cline{1-4}
\multicolumn{4}{p{5in}}{}\\
\end{tabular}\\ 
